Share Email Print

Proceedings Paper

Photonic switching for reliable nanoscale three-dimensional integrated network-on-chips
Author(s): Ivan B. Djordjevic
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

As the multi-core architecture is becoming a prevailing high-performance chip design approach, power efficiency, limited bandwidth and low reliability have been recognized as major communication bottlenecks for on-chip networks (NOCs). To simultaneously tackle the above problems, we propose a three-dimensional integrated (3DI) photonic NOC architecture. This architecture is composed of the following layers: (i) the multi-core processor layer that host multiple heterogeneous processing cores together with corresponding local memories and network interfaces, (ii) multiple 3D memory layers that provide the bulk of on-chip memory, and (iii) photonic NOC layer. The photonic NOC layer is based on the optical cross-point switches (OXSs) implemented using active vertical coupler (AVC) structures. The use of this photonic NOC layer will provide ample bandwidth at reduced latencies along with low power consumption. The nanoscale photonic NOCs are sensitive to process variation and reliability issues. To deal with these problems, we proposed the use of LDPC codes with decoding based on simple majority-logic.

Paper Details

Date Published: 19 January 2011
PDF: 8 pages
Proc. SPIE 7944, Optoelectronic Interconnects and Component Integration XI, 79440U (19 January 2011); doi: 10.1117/12.873322
Show Author Affiliations
Ivan B. Djordjevic, The Univ. of Arizona (United States)

Published in SPIE Proceedings Vol. 7944:
Optoelectronic Interconnects and Component Integration XI
Alexei L. Glebov; Ray T. Chen, Editor(s)

© SPIE. Terms of Use
Back to Top
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?