In this paper, a high-speed CMOS image sensor having a new architecture and a new operating principle has been developed. The image sensor achieves both the continuous capturing and the burst capturing by a single chip, and has low power consumption, low heat generation, high sensitivity and high S/N ratio. This image sensor consist of mainly four blocks, two dimensional pixel array of 4-transister CMOS active pixel, analog memory arrays connected with each pixel output line independently to the pixel array, scanning circuits and multiple number of output amplifiers. A prototype image sensor was fabricated using a 0.18μm 2-Poly 3-Metal CMOS technology with the die size of 5550 μm^H x 4575 μm^V, the pixel size of 48 μm^H x 48 μm^V, the number of pixels of 72^H x 32^V, the number of analog memories of 104 memories per pixel and the 6 parallel horizontal output circuits and output amplifiers. The aperture ratio is 35% and the conversion gain is 60 μV/e-(input referred). It has been confirmed that this image sensor achieves 10,000,000 fps during burst capturing mode and 10,000 fps during the continuous capturing mode through the image capture experiments of high speed phenomena such as rotating object and discharge phenomenon.

Date Published: 24 January 2011
PDF: 8 pages
Proc. SPIE 7876, Digital Photography VII, 78760G (24 January 2011); doi: 10.1117/12.872207

Published in SPIE Proceedings Vol. 7876:
Digital Photography VII
Francisco H. Imai; Feng Xiao, Editor(s)