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Proceedings Paper

OPC verification and hotspot management for yield enhancement through layout analysis
Author(s): Gyun Yoo; Jungchan Kim; Taehyeong Lee; Areum Jung; Hyunjo Yang; Donggyu Yim; Sungki Park; Kotaro Maruyama; Masahiro Yamamoto; Abhishek Vikram; Sangho Park
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Paper Abstract

As the design rule shrinks down, various techniques such as RET, DFM have been continuously developed and applied to lithography field. And we have struggled not only to obtain sufficient process window with those techniques but also to feedback hot spots to OPC process for yield improvement in mass production. OPC verification procedure which iterates its processes from OPC to wafer verification until the CD targets are met and hot spots are cleared is becoming more important to ensure robust and accurate patterning and tight hot spot management. Generally, wafer verification results which demonstrate how well OPC corrections are made need to be fed back to OPC engineer in effective and accurate way. First of all, however, it is not possible to cover all transistors in full-chip with some OPC monitoring points which have been used for wafer verification. Secondly, the hot spots which are extracted by OPC simulator are not always reliable enough to represent defective information for full-chip. Finally, it takes much TAT and labor to do this with CD SEM measurement. These difficulties on wafer verification would be improved by design based analysis. The optimal OPC monitoring points are created by classifying all transistors in full chip layout and Hotspot set is selected by pattern matching process using the NanoScopeTM, which is known as a fast design based analysis tool, with a very small amount of hotspots extracted by OPC simulator in full chip layout. Then, each set is used for wafer verification using design based inspection tool, NGR2150TM. In this paper, new verification methodology based on design based analysis will be introduced as an alternative method for effective control of OPC accuracy and hot spot management.

Paper Details

Date Published: 20 April 2011
PDF: 11 pages
Proc. SPIE 7971, Metrology, Inspection, and Process Control for Microlithography XXV, 79710H (20 April 2011); doi: 10.1117/12.870395
Show Author Affiliations
Gyun Yoo, Hynix Semiconductor Inc. (Korea, Republic of)
Jungchan Kim, Hynix Semiconductor Inc. (Korea, Republic of)
Taehyeong Lee, Hynix Semiconductor Inc. (Korea, Republic of)
Areum Jung, Hynix Semiconductor Inc. (Korea, Republic of)
Hyunjo Yang, Hynix Semiconductor Inc. (Korea, Republic of)
Donggyu Yim, Hynix Semiconductor Inc. (Korea, Republic of)
Sungki Park, Hynix Semiconductor Inc. (Korea, Republic of)
Kotaro Maruyama, NanoGeometry Research Inc. (Japan)
Masahiro Yamamoto, NanoGeometry Research Inc. (Japan)
Abhishek Vikram, Anchor Semiconductor, Inc. (United States)
Sangho Park, Daouxilicon Inc. (Korea, Republic of)

Published in SPIE Proceedings Vol. 7971:
Metrology, Inspection, and Process Control for Microlithography XXV
Christopher J. Raymond, Editor(s)

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