Share Email Print

Proceedings Paper

High throughput VLSI architecture for multiresolution integer motion estimation in high definition AVS video encoder
Author(s): HaiBing Yin; Honggang Qi; Hao Xu; Xiaodong Xie; Wen Gao
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

This paper proposes a hardware friendly multi-resolution motion estimation algorithm and VLSI architecture for high definition MPEG-like video encoder hardware implementation. By parallel searching and utilizing the high correlation in multi-resolution reference pixels, huge throughput and computation due to large search window are alleviated considerably. Sixteen way parallel processing element arrays with configurable multiplying technologies achieve fast search with regular data access and efficient data reuse. Also, the parallel arrays can be efficiently reused at three hierarchical levels for sequential motion vector refinement. The modified algorithm reaches a good balance between implementation complexity and search performance. Also, the logic circuit and on-chip SRAM consumption of the VLSI architecture are moderate.

Paper Details

Date Published: 4 August 2010
PDF: 10 pages
Proc. SPIE 7744, Visual Communications and Image Processing 2010, 77441W (4 August 2010); doi: 10.1117/12.863475
Show Author Affiliations
HaiBing Yin, China Jiliang Univ. (China)
Peking Univ. (China)
Honggang Qi, Peking Univ. (China)
Hao Xu, Peking Univ. (China)
Xiaodong Xie, Peking Univ. (China)
Wen Gao, Peking Univ. (China)

Published in SPIE Proceedings Vol. 7744:
Visual Communications and Image Processing 2010
Pascal Frossard; Houqiang Li; Feng Wu; Bernd Girod; Shipeng Li; Guo Wei, Editor(s)

© SPIE. Terms of Use
Back to Top
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?