Share Email Print

Proceedings Paper

Cycle-accurate evaluation of reconfigurable photonic networks-on-chip
Author(s): Christof Debaes; Iñigo Artundo; Wim Heirman; Jan Van Campenhout; Hugo Thienpont
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

There is little doubt that the most important limiting factors of the performance of next-generation Chip Multiprocessors (CMPs) will be the power efficiency and the available communication speed between cores. Photonic Networks-on-Chip (NoCs) have been suggested as a viable route to relieve the off- and on-chip interconnection bottleneck. Low-loss integrated optical waveguides can transport very high-speed data signals over longer distances as compared to on-chip electrical signaling. In addition, with the development of silicon microrings, photonic switches can be integrated to route signals in a data-transparent way. Although several photonic NoC proposals exist, their use is often limited to the communication of large data messages due to a relatively long set-up time of the photonic channels. In this work, we evaluate a reconfigurable photonic NoC in which the topology is adapted automatically (on a microsecond scale) to the evolving traffic situation by use of silicon microrings. To evaluate this system's performance, the proposed architecture has been implemented in a detailed full-system cycle-accurate simulator which is capable of generating realistic workloads and traffic patterns. In addition, a model was developed to estimate the power consumption of the full interconnection network which was compared with other photonic and electrical NoC solutions. We find that our proposed network architecture significantly lowers the average memory access latency (35% reduction) while only generating a modest increase in power consumption (20%), compared to a conventional concentrated mesh electrical signaling approach. When comparing our solution to high-speed circuit-switched photonic NoCs, long photonic channel set-up times can be tolerated which makes our approach directly applicable to current shared-memory CMPs.

Paper Details

Date Published: 17 May 2010
PDF: 11 pages
Proc. SPIE 7719, Silicon Photonics and Photonic Integrated Circuits II, 771916 (17 May 2010); doi: 10.1117/12.854744
Show Author Affiliations
Christof Debaes, Vrije Univ. Brussel (Belgium)
Iñigo Artundo, Univ. Politécnica de Valencia (Spain)
Wim Heirman, Univ. Gent (Belgium)
Jan Van Campenhout, Univ. Gent (Belgium)
Hugo Thienpont, Vrije Univ. Brussel (Belgium)

Published in SPIE Proceedings Vol. 7719:
Silicon Photonics and Photonic Integrated Circuits II
Giancarlo Cesare Righini, Editor(s)

© SPIE. Terms of Use
Back to Top
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?