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Proceedings Paper

An analytic formula for determination of simulation runs for analysis of VLSI circuits
Author(s): Xinjia Chen; Pradeep Bhattacharya; Ernest Walker; Jiecai Luo
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Paper Abstract

In this article, an explicit formula is derived for determining appropriate number of simulation runs to estimate the parametric yield or violation probability of VLSI circuits. The formula involves no approximation and thus offers a rigorous control of the statistical error of estimation. Moreover, the formula is substantially less conservative than existing methods and hence can be used to avoid unnecessary computation. The application of the formula is illustrated by the timing analysis of an n-input NAND gate with a capacitive load.

Paper Details

Date Published: 5 May 2010
PDF: 12 pages
Proc. SPIE 7679, Micro- and Nanotechnology Sensors, Systems, and Applications II, 76792F (5 May 2010); doi: 10.1117/12.852500
Show Author Affiliations
Xinjia Chen, Southern Univ. (United States)
Pradeep Bhattacharya, Southern Univ. (United States)
Ernest Walker, Southern Univ. (United States)
Jiecai Luo, Southern Univ. (United States)

Published in SPIE Proceedings Vol. 7679:
Micro- and Nanotechnology Sensors, Systems, and Applications II
Thomas George; M. Saif Islam; Achyut Kumar Dutta, Editor(s)

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