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Proceedings Paper

Litho and patterning challenges for memory and logic applications at the 22-nm node
Author(s): Jo Finders; Mircea Dusa; Peter Nikolsky; Youri van Dommelen; Robert Watso; Tom Vandeweyer; Joost Beckaert; Bart Laenens; Lieve Van Look
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Paper Abstract

In this paper we look into the litho and patterning challenges at the 22nm node. These challenges are different for memory and logic applications driven by the difference in device layout. In the case of memory, very small pitches and CDs have to be printed, close to the optical diffraction limit (k1) and resist resolution capability. For random logic applications e.g. the printing of SRAM, real pitch splitting techniques have to be applied for the first time at the 22nm node due to the aggressive dimensions of extreme small and compact area and pitch of SRAM bitcell. Common challenges are found for periphery of memory and random logic SRAM cells: here the Best Focus difference per feature type, limits the Usable Depth of Focus.

Paper Details

Date Published: 22 March 2010
PDF: 10 pages
Proc. SPIE 7640, Optical Microlithography XXIII, 76400C (22 March 2010); doi: 10.1117/12.848330
Show Author Affiliations
Jo Finders, ASML (Netherlands)
Mircea Dusa, ASML US Inc. (Netherlands)
Peter Nikolsky, ASML (Netherlands)
Youri van Dommelen, ASML (Netherlands)
Robert Watso, ASML Albany (United States)
Tom Vandeweyer, IMEC vzw (Belgium)
Joost Beckaert, IMEC vzw (Belgium)
Bart Laenens, IMEC vzw (Belgium)
Lieve Van Look, IMEC vzw (Belgium)

Published in SPIE Proceedings Vol. 7640:
Optical Microlithography XXIII
Mircea V. Dusa; Will Conley, Editor(s)

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