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Proceedings Paper

DRCPlus in a router: automatic elimination of lithography hotspots using 2D pattern detection and correction
Author(s): Jie Yang; Norma Rodriguez; Olivier Omedes; Frank Gennari; Ya-Chieh Lai; Viral Mankad
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Paper Abstract

As technology processes continue to shrink, standard design rule checking (DRC) has become insufficient to guarantee design manufacturability. DRCPlus is a powerful technique for capturing yield detractors related to complex 2D situations1,2. DRCPlus is a pattern-based 2D design rule check beyond traditional width and space DRC that can identify problematic 2D configurations which are difficult to manufacture. This paper describes a new approach for applying DRCPlus in a router, enabling an automated approach to detecting and fixing known lithography hotspots using an integrated fast 2D pattern matching engine. A simple pass/no-pass criterion associated with each pattern offers designers guidance on how to fix these problematic patterns. Since it does not rely on compute intensive simulations, DRCPlus can be applied on fairly large design blocks and enforced in conjunction with standard DRC in the early stages of the design flow. By embedding this capability into the router, 2D yield detractors can be identified and fixed by designers in a push-button manner without losing design connectivity. More robust designs can be achieved and the impact on parasitics can be easily assessed. This paper will describe a flow using a fast 2D pattern matching engine integrated into the router in order to enforce DRCPlus rules. An integrated approach allows for rapid identification of hotspot patterns and, more importantly, allows for rapid fixing and verification of these hotspots by a tool that understands design intent and constraints. The overall flow is illustrated in Figure 1. An inexact search pattern is passed to the integrated pattern matcher. The match locations are filtered by the router through application of a DRC constraint (typically a recommended rule). Matches that fail this constraint are automatically fixed by the router, with the modified regions incrementally re-checked to ensure no additional DRCPlus violations are introduced.

Paper Details

Date Published: 2 April 2010
PDF: 7 pages
Proc. SPIE 7641, Design for Manufacturability through Design-Process Integration IV, 76410Q (2 April 2010); doi: 10.1117/12.846650
Show Author Affiliations
Jie Yang, Advanced Micro Devices, Inc. (United States)
Norma Rodriguez, Advanced Micro Devices, Inc. (United States)
Olivier Omedes, Cadence Design Systems, Inc. (United States)
Frank Gennari, Cadence Design Systems, Inc. (United States)
Ya-Chieh Lai, Cadence Design Systems, Inc. (United States)
Viral Mankad, Cadence Design Systems, Inc. (United States)

Published in SPIE Proceedings Vol. 7641:
Design for Manufacturability through Design-Process Integration IV
Michael L. Rieger; Joerg Thiele, Editor(s)

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