In the fabrication of interconnect test chips with a half pitch of 35 nm, we used an EUV full-field scanner (EUV1) for three critical layers: Metal 1, Via 1 and Metal 2. In this study, we focused on the Via-1 layer and investigated the printing characteristics of 35-nm via-hole patterns. There are three types of major via-hole patterns; aligned, staggered, and isolated. Simple optical proximity effect correction (OPC) and shadowing effect correction (SEC) were applied to the mask patterns to reduce the iso-dense bias and anisotropy of hole shapes. Mask critical-dimension (CD) correction enabled the fabrication of all three types of patterns with almost the same CD. A simulation analysis revealed the mask error enhancement factor (MEEF) to be about 2.5, the exposure latitude to be about 18%, and the depth of focus (DOF) to be about 100 nm for 35-nm via holes when the resist CD was 35 nm. The experimental results agree fairly well with the simulation results. The intra-field CD uniformity of 35-nm via holes is 3.3 nm (3σ). The intra-field overlay accuracy (Mean+3σ) between the Via-1 and Metal-2 layers is better than 15 nm. We used a multi-stacked resist to fabricate 35-nm via holes in a low-k dielectric layer. Moreover, we fabricated interconnect test chips and measured their electrical properties. The resistance of 32-nm vias is 12.4Ω, which meets the target of International Technology Roadmap for Semiconductors (ITRS). The yield of 40k dense via chains was over 70%. The results demonstrate that EUV lithography is useful for the fabrication of ULSI devices with a half pitch of 35 nm and beyond.

Date Published: 22 March 2010
PDF: 12 pages
Proc. SPIE 7636, Extreme Ultraviolet (EUV) Lithography, 76362D (22 March 2010); doi: 10.1117/12.846315

Published in SPIE Proceedings Vol. 7636:
Extreme Ultraviolet (EUV) Lithography
Bruno M. La Fontaine, Editor(s)