Share Email Print

Proceedings Paper

A scalable multi-FPGA framework for real-time digital signal processing
Author(s): K. M. Irick; M. DeBole; S. Park; A. Al Maashri; S. Kestur; C.-L. Yu; N. Vijaykrishnan
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

FPGAs have emerged as the preferred platform for implementing real-time signal processing applications. In the sub-45nm technologies, FPGAs offer significant cost and design-time advantages over application-specific custom chips and consume significantly less power than general-purpose processors while maintaining, or improving performance. Moreover, FPGAs are more advantageous than GPUs in their support for control-intensive applications, custom bit-precision operations, and diverse system interface protocols. Nonetheless, a significant inhibitor to the widespread adoption of FPGAs has been the expertise required to effectively realize functional designs that maximize application performance. While there have been several academic and commercial efforts to improve the usability of FPGAs, they have primarily focused on easing the tasks of an expert FPGA designer rather than increasing the usability offered to an application developer. In this work, the design of a scalable algorithmic-level design framework for FPGAs, AlgoFLEX, is described. AlgoFLEX offers rapid algorithmic level composition and exploration while maintaining the performance realizable from a fully custom, albeit difficult and laborious, design effort. The framework masks aspects of accelerator implementation, mapping, and communication while exposing appropriate algorithm tuning facilities to developers and system integrators. The effectiveness of the AlgoFLEX framework is demonstrated by rapidly mapping a class of image and signal processing applications to a multi-FPGA platform.

Paper Details

Date Published: 2 September 2009
PDF: 6 pages
Proc. SPIE 7444, Mathematics for Signal and Information Processing, 744416 (2 September 2009); doi: 10.1117/12.834177
Show Author Affiliations
K. M. Irick, The Pennsylvania State Univ. (United States)
M. DeBole, The Pennsylvania State Univ. (United States)
S. Park, The Pennsylvania State Univ. (United States)
A. Al Maashri, The Pennsylvania State Univ. (United States)
S. Kestur, The Pennsylvania State Univ. (United States)
C.-L. Yu, Arizona State Univ. (United States)
N. Vijaykrishnan, The Pennsylvania State Univ. (United States)

Published in SPIE Proceedings Vol. 7444:
Mathematics for Signal and Information Processing
Franklin T. Luk; Mark S. Schmalz; Gerhard X. Ritter; Junior Barrera; Jaakko T. Astola, Editor(s)

© SPIE. Terms of Use
Back to Top
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?