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Proceedings Paper

Future memory technologies
Author(s): Wolfgang Mueller; Michael Kund
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Paper Abstract

In this paper the concepts, status and technical challenges for high density working memory will be reviewed. The main technology covering this application space today is DRAM, based on a 1 transistor 1 capacitor cell (1T1C). 50-60nm DRAM technologies have been already introduced into mass production. Full process integration results for 40nm DRAM, and key technologies for the 30nm DRAM node have been presented previously. No technical roadblock is seen for further scaling down to the 30nm node, however some of the key technology concepts such as the capacitor dielectrics with capacitance equivalent (oxide) thickness (CET) of <0.5nm have still to be proven. The DRAM cell sizes currently in mass production are ranging between 8F2 and 6F2. The development of the further cell size reduction to 4F2 is under development. The status and scaling potential of the most probable DRAM successor candidate technologies: capacitor-less DRAM, phase-change RAM (PCRAM), and spin transfer torque MRAM (STT MRAM) will be discussed. Capacitor-less DRAM or floating body FB DRAM cells have been proposed, both for stand-alone memory and embedded memory applications. Different cell device schemes (transistor and capacitor-coupled thyristor) have been investigated. Recently a number of papers covering cell device data and integration schemes for 50nm feature sizes have been published. However so far no results based on a high density demonstrator chip or product have been shown. PCRAM is the most mature technology out of the candidates mentioned. Product demonstrators with 90nm design rules and densities up to 512Mb have been presented. The introduction of first products in 65-45nm technology for 2009 has been announced recently. Scalability of the phase change element to below 10nm has been demonstrated. Spin transfer torque (STT) MRAM has been proposed as a fast, nonvolatile, and scalable cell concept. The memory concept has been experimentally verified at structure sizes down to 50nm. Theoretical estimations indicate the scalability down to 20nm. A 2Mb product demonstrator has been published, utilizing a rather large cell size, however. Based on these data the comparison of the key parameters for the different technologies will be presented, and a mapping of the different technologies to the current DRAM application segments will be proposed.

Paper Details

Date Published: 28 May 2009
PDF: 13 pages
Proc. SPIE 7363, VLSI Circuits and Systems IV, 736302 (28 May 2009); doi: 10.1117/12.833031
Show Author Affiliations
Wolfgang Mueller, Qimonda Dresden GmbH & Co. OHG (Germany)
Michael Kund, Qimonda AG (Germany)

Published in SPIE Proceedings Vol. 7363:
VLSI Circuits and Systems IV
Teresa Riesgo; Eduardo de la Torre; Leandro Soares Indrusiak, Editor(s)

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