As the demand of higher image quality and greater processing capabilities are growing, obtaining higher data bandwidth for on-chip processing is becoming a more and more important issue. DMA (Direct Memory Access) component, as the key element in stream processing SoC (System on Chip) [1], should be deeply researched and designed to satisfy the high data bandwidth requirement of processing units. In this paper, we introduce a scalable high-performance DMA architecture for complex SoC to satisfy rigorous high sustained bandwidth and versatile functionality requirements. Several techniques and structures are proposed in this paper. An integrated verification environment is also built for our design to fully verify its functionality. And the performance improvement by using our architecture is analyzed. At the end of the paper, the post-simulation and tape-out results are provided. The whole implementation has been silicon proven to be functional and efficient.

Date Published: 30 October 2009
PDF: 7 pages
Proc. SPIE 7497, MIPPR 2009: Medical Imaging, Parallel Processing of Images, and Optimization Techniques, 749708 (30 October 2009); doi: 10.1117/12.833019

Published in SPIE Proceedings Vol. 7497:
MIPPR 2009: Medical Imaging, Parallel Processing of Images, and Optimization Techniques
Faxiong Zhang; Faxiong Zhang, Editor(s)