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Proceedings Paper

A design of complex square root for FPGA implementation
Author(s): Dong Wang; Milos D. Ercegovac
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Paper Abstract

We present a design for FPGA implementation of a complex square root algorithm for fixed-point operands in radix-4 representation. The design consists of (i) argument prescaling, (ii) residual recurrence, and (iii) result postscaling. These parts share logic resources and optimize the use of resources on FPGA devices used for implementation. Table building methods for prescaling and postscaling are analyzed and efficient designs approaches are discussed. The design is implemented in Altera Stratix-II FPGA for several argument precisions and compared in cost, latency and power with a design with an IP-based design. The results show advantages of the proposed design in cost, delay, and power.

Paper Details

Date Published: 3 September 2009
PDF: 11 pages
Proc. SPIE 7444, Mathematics for Signal and Information Processing, 74440L (3 September 2009); doi: 10.1117/12.831235
Show Author Affiliations
Dong Wang, Xi'an Jiaotong Univ. (China)
Milos D. Ercegovac, Univ. of California, Los Angeles (United States)

Published in SPIE Proceedings Vol. 7444:
Mathematics for Signal and Information Processing
Franklin T. Luk; Mark S. Schmalz; Gerhard X. Ritter; Junior Barrera; Jaakko T. Astola, Editor(s)

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