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Proceedings Paper

A new approach to accelerate SEU sensitivity evaluation in circuits with embedded memories
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Paper Abstract

Current circuit complexity requires faster fault injection techniques to allow the evaluation of a high number of faults in a reasonable time. In particular, FPGA emulation has proven to be a performance effective method to analyze the behavior of digital circuits in the presence of soft errors due to SEU effects. In general, fault emulation-based solutions that use circuit instrumentation to inject faults in the literature does not consider the fault emulation in circuits with embedded memories. The few existing proposals that study this kind of circuits are oriented to inject faults in microprocessors, are slow solutions with respect to the injection in flip-flops and with a poor capacity to analyze the circuit behavior, due to the limited accessibility in memories (a word memory per clock cycle). Embedded memories are more and more usual and large in modern designs, and therefore, the emulation of the embedded memories is a problem of rising importance. The proposed models presented in this work allow the fault emulation in embedded memories, injection faults and observing their effects in a fast way.

Paper Details

Date Published: 28 May 2009
PDF: 9 pages
Proc. SPIE 7363, VLSI Circuits and Systems IV, 73630X (28 May 2009); doi: 10.1117/12.822057
Show Author Affiliations
M. Portela-García, Univ. Carlos III de Madrid (Spain)
M. Garcia Valderas, Univ. Carlos III de Madrid (Spain)
C. Lopez-Ongil, Univ. Carlos III de Madrid (Spain)
L. Entrena, Univ. Carlos III de Madrid (Spain)

Published in SPIE Proceedings Vol. 7363:
VLSI Circuits and Systems IV
Teresa Riesgo; Eduardo de la Torre; Leandro Soares Indrusiak, Editor(s)

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