Share Email Print

Proceedings Paper

Cache-aware network-on-chip for chip multiprocessors
Author(s): Konstantinos Tatas; Costas Kyriacou; George Dekoulis; Demetris Demetriou; Costas Avraam; Anastasia Christou
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

This paper presents the hardware prototype of a Network-on-Chip (NoC) for a chip multiprocessor that provides support for cache coherence, cache prefetching and cache-aware thread scheduling. A NoC with support to these cache related mechanisms can assist in improving systems performance by reducing the cache miss ratio. The presented multi-core system employs the Data-Driven Multithreading (DDM) model of execution. In DDM thread scheduling is done according to data availability, thus the system is aware of the threads to be executed in the near future. This characteristic of the DDM model allows for cache aware thread scheduling and cache prefetching. The NoC prototype is a crossbar switch with output buffering that can support a cache-aware 4-node chip multiprocessor. The prototype is built on the Xilinx ML506 board equipped with a Xilinx Virtex-5 FPGA.

Paper Details

Date Published: 28 May 2009
PDF: 8 pages
Proc. SPIE 7363, VLSI Circuits and Systems IV, 73630N (28 May 2009); doi: 10.1117/12.821695
Show Author Affiliations
Konstantinos Tatas, Frederick Univ. (Cyprus)
Costas Kyriacou, Frederick Univ. (Cyprus)
George Dekoulis, Lancaster Univ. (United Kingdom)
Demetris Demetriou, Frederick Univ. (Cyprus)
Costas Avraam, Frederick Univ. (Cyprus)
Anastasia Christou, Frederick Univ. (Cyprus)

Published in SPIE Proceedings Vol. 7363:
VLSI Circuits and Systems IV
Teresa Riesgo; Eduardo de la Torre; Leandro Soares Indrusiak, Editor(s)

© SPIE. Terms of Use
Back to Top
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?