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Proceedings Paper

Improved 10GBase-LX4 limiting amplifier in a low-cost 0.18 µm CMOS technology
Author(s): J. M. García del Pozo; S. Celma; A. Otín
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Paper Abstract

This work overcomes the limitations of a previous work by using three high frequency compensation techniques: polezero cancellation, shunt-peaking and downscaling. By considering these strategies, a fully integrated limiting amplifier in a low-cost 0.18 μm CMOS digital process is introduced. This design improves the original design without inductors and without local multi-feedback loops obtaining a compact, stable and robust design perfectly intended for low-voltage applications.

Paper Details

Date Published: 28 May 2009
PDF: 10 pages
Proc. SPIE 7363, VLSI Circuits and Systems IV, 73630D (28 May 2009); doi: 10.1117/12.821369
Show Author Affiliations
J. M. García del Pozo, Univ. of Zaragoza (Spain)
S. Celma, Univ. of Zaragoza (Spain)
A. Otín, Univ. of Zaragoza (Spain)

Published in SPIE Proceedings Vol. 7363:
VLSI Circuits and Systems IV
Teresa Riesgo; Eduardo de la Torre; Leandro Soares Indrusiak, Editor(s)

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