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Proceedings Paper

Static power dissipation in adder circuits: the UDSM domain
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Paper Abstract

This paper presents adder circuits of various architectures aimed at reducing static power dissipation. Circuit topologies for basic building blocks were evaluated for fabrication technologies of 65nm down to 32nm, and simulation results are presented. This work has lead to the development of various low power adder circuits and provides comparative analysis leading to the recommendation that a variable size block carry select adder is the best performer, taking into consideration both static and dynamic power dissipation.

Paper Details

Date Published: 28 May 2009
PDF: 11 pages
Proc. SPIE 7363, VLSI Circuits and Systems IV, 736311 (28 May 2009); doi: 10.1117/12.819798
Show Author Affiliations
Steve Cayouette, Royal Military College of Canada (Canada)
Dhamin Al-Khalili, Royal Military College of Canada (Canada)


Published in SPIE Proceedings Vol. 7363:
VLSI Circuits and Systems IV
Teresa Riesgo; Eduardo de la Torre; Leandro Soares Indrusiak, Editor(s)

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