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Proceedings Paper

A low voltage CMOS low drop-out voltage regulator
Author(s): Salma Ali Bakr; Tanvir Ahmad Abbasi; Mohammas Suhaib Abbasi; Mohamed Samir Aldessouky; Mohammad Usaid Abbasi
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Paper Abstract

A low voltage implementation of a CMOS Low Drop-Out voltage regulator (LDO) is presented. The requirement of low voltage devices is crucial for portable devices that require extensive computations in a low power environment. The LDO is implemented in 90nm generic CMOS technology. It generates a fixed 0.8V from a 2.5V supply which on discharging goes to 1V. The buffer stage used is unity gain configured unbuffered OpAmp with rail-to-rail swing input stage. The simulation result shows that the implemented circuit provides load regulation of 0.004%/mA and line regulation of -11.09mV/V. The LDO provides full load transient response with a settling time of 5.2μs. Further, the dropout voltage is 200mV and the quiescent current through the pass transistor (Iload=0) is 20μA. The total power consumption of this LDO (excluding bandgap reference) is only 80μW.

Paper Details

Date Published: 28 May 2009
PDF: 7 pages
Proc. SPIE 7363, VLSI Circuits and Systems IV, 73630S (28 May 2009); doi: 10.1117/12.819796
Show Author Affiliations
Salma Ali Bakr, IMEC (Belgium)
Tanvir Ahmad Abbasi, Jamia Millia Islamia (India)
Mohammas Suhaib Abbasi, SRM Univ. (India)
Mohamed Samir Aldessouky, Si-Ware Systems (Egypt)
Mohammad Usaid Abbasi, Freescale Semiconductor (India)

Published in SPIE Proceedings Vol. 7363:
VLSI Circuits and Systems IV
Teresa Riesgo; Eduardo de la Torre; Leandro Soares Indrusiak, Editor(s)

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