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Proceedings Paper

Common hardware-in-the-loop development
Author(s): Hajin J. Kim; Stephen G. Moss
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Paper Abstract

An approach to streamline the Hardware-In-the-Loop (HWIL) simulation development process is under evaluation. With increased microprocessor speed, FPGA capacity and increased bus bandwidth over the last decade, a common interface design may be able to support a large number of HWIL interfaces that were previously custom designed interfaces. The Common HWIL approach will attempt to provide a more flexible, scalable system. The overall goal of the Common HWIL system will be to reduce cost by minimizing redundant development and operational labor and equipment expenses. This paper will present current results and future plans of the development.

Paper Details

Date Published: 22 April 2009
PDF: 8 pages
Proc. SPIE 7301, Technologies for Synthetic Environments: Hardware-in-the-Loop Testing XIV, 730107 (22 April 2009); doi: 10.1117/12.819194
Show Author Affiliations
Hajin J. Kim, U.S. Army RDECOM (United States)
Stephen G. Moss, AEgis Technologies Group, Inc. (United States)

Published in SPIE Proceedings Vol. 7301:
Technologies for Synthetic Environments: Hardware-in-the-Loop Testing XIV
James A. Buford Jr.; Robert Lee Murrer Jr., Editor(s)

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