Share Email Print

Proceedings Paper

Convergent automated chip level lithography checking and fixing at 45nm
Author(s): Valerio Perez; Shyue Fong Quek; Sky Yeo; Colin Hui; Kuang Kuo Lin; Walter Ng; Michel Cote; Bala Kasthuri; Philippe Hurat; Matt A. Thompson; Chi-Min Yuan; Puneet Sharma
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

To provide fabless designers the same advantage as Integrated Device Manufacturer (IDMs), a design-oriented litho model has been calibrated and an automated lithography (litho) hotspot detection and fixing flow has been implemented during final routing optimization. This paper shows how a design-oriented litho model was built and used to automate a litho hotspot fixing design flow. The model, calibrated and validated against post-OPC contour data at 99%, was embedded into a Litho Physical Analyzer (LPA) tech file. It allowed the litho contour of drawn layouts to be simulated at full chip level to detect litho hotspots and to provide fixing guidelines. Automated hotspots fixing was hence made possible by feeding the guidelines to the fixing tools in an industry based integrated flow. Post-fixing incremental checks were also performed to converge to a clean design.

Paper Details

Date Published: 12 March 2009
PDF: 10 pages
Proc. SPIE 7275, Design for Manufacturability through Design-Process Integration III, 72751S (12 March 2009); doi: 10.1117/12.816593
Show Author Affiliations
Valerio Perez, Chartered Semiconductor Manufacturing, Ltd. (Singapore)
Shyue Fong Quek, Chartered Semiconductor Manufacturing, Ltd. (Singapore)
Sky Yeo, Chartered Semiconductor Manufacturing, Ltd. (Singapore)
Colin Hui, Chartered Semiconductor Manufacturing, Ltd. (Singapore)
Kuang Kuo Lin, Chartered Semiconductor Manufacturing, Ltd. (Singapore)
Walter Ng, Chartered Semiconductor Manufacturing, Ltd. (Singapore)
Michel Cote, Cadence Design Systems, Inc. (United States)
Bala Kasthuri, Cadence Design Systems, Inc. (United States)
Philippe Hurat, Cadence Design Systems, Inc. (United States)
Matt A. Thompson, Freescale Semiconductor, Inc. (United States)
Chi-Min Yuan, Freescale Semiconductor, Inc. (United States)
Puneet Sharma, Freescale Semiconductor, Inc. (United States)

Published in SPIE Proceedings Vol. 7275:
Design for Manufacturability through Design-Process Integration III
Vivek K. Singh; Michael L. Rieger, Editor(s)

© SPIE. Terms of Use
Back to Top
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?