During the deep sub-micron semiconductor manufacturing process, the Chemical-Mechanical Polishing (CMP) is applied on conductor layers to create a planar surface over the wafer. To ensure layer uniformity after CMP and to avoid metal dishing and erosion effects, dummy metals are usually inserted to the layers either by designers or foundries. However, adding dummy metal polygons can have undesirable impact to the capacitance and hence the timings of the clock paths and signal paths in the design. Chartered and Magma jointly developed and validated a methodology combining the router timing-aware track fill followed by foundry metal fill to minimize the timing impact of the metal fill to the design as well as achieving high quality copper uniformity. In this paper, we will show the proposed metal fill methodology outperform the conventional approaches of metal fill or track fill. The proposed metal fill was validated using Static Timing Analysis and an accurate silicon calibrated CMP model is used for copper (Cu) thickness distributions comparisons. From the 65nm case study results, the timing impact to the design in terms of total number of nets with slack degradation has been reduced from 4% to 0.24%. And the copper uniformity in terms of standard deviation of the copper density has been improved from 0.192 to 0.142 on average. The deployment of proposed metal fill is integrated seamlessly into the reference design flow.

Date Published: 12 March 2009
PDF: 8 pages
Proc. SPIE 7275, Design for Manufacturability through Design-Process Integration III, 72751P (12 March 2009); doi: 10.1117/12.816476

Published in SPIE Proceedings Vol. 7275:
Design for Manufacturability through Design-Process Integration III
Vivek K. Singh; Michael L. Rieger, Editor(s)