In state of the art integrated circuit industry for transistors gate length of 45nm and beyond, the sharp distinction between design and fabrication phases is becoming inadequate for fast product development. Lithographical information along with design rules has to be passed from foundries to designers, as these effects have to be taken into consideration during the design stage to insure a Lithographically Friendly Design, which in turn demands new communication channels between designers and foundries to provide the needed litho information. In the case of fabless design houses this requirement is faced with some problems like incompatible EDA platforms at both ends, and confidential information that can not be revealed by the foundry back to the design house. In this paper we propose a framework in which we will try to demonstrate a systematic approach to match any lithographical OPC solution from different EDA vendors into CalibreTM. The goal is to export how the design will look on wafer from the foundry to the designers without saying how, or requiring installation of same EDA tools. In the developed framework, we will demonstrate the flow used to match all steps used in developing OPC starting from the lithography modeling and going through the OPC recipe. This is done by the use of automated scripts that characterizes the existing OPC foundry solution, and identifies compatible counter parts in the CalibreTM domain to generate an encrypted package that can be used at the designers' side. Finally the framework will be verified using a developed test case.

Date Published: 12 March 2009
PDF: 11 pages
Proc. SPIE 7275, Design for Manufacturability through Design-Process Integration III, 72751O (12 March 2009); doi: 10.1117/12.816281

Published in SPIE Proceedings Vol. 7275:
Design for Manufacturability through Design-Process Integration III
Vivek K. Singh; Michael L. Rieger, Editor(s)