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Proceedings Paper

Large-scale double-patterning compliant layouts for DP engine and design rule development
Author(s): Christopher Cork; Kevin Lucas; John Hapli; Herve Raffard; Levi Barnes
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Paper Abstract

Double Patterning is seen as the prime technology to keep Moore's law on path while EUV technology is still maturing into production worthiness. As previously seen for alternating-Phase Shift Mask technology[1], layout compliance of double patterning is not trivial [2,3] and blind shrinks of anything but the most simplistic existing layouts, will not be directly suitable for double patterning. Evaluating a production worthy double patterning engine with highly non-compliant layouts would put unrealistic expectations on that engine and provide metrics with poor applicability for eventual large designs. The true production use-case would be for designs that have at least some significant double patterning compliance already enforced at the design stage. With this in mind a set of ASIC design blocks of different sizes and complexities were created that were double patterning compliant. To achieve this, a set of standard cells were generated, which individually and in isolation were double patterning compliant, for multiple layers simultaneously. This was done using the automated Standard Cell creation tool CadabraTM [4]. To create a full ASIC, however, additional constraints were added to make sure compliance would not be broken across the boundaries between standard cells when placed next to each other [5]. These standard cells were then used to create a variety of double patterning compliant ASICs using iCCompilerTM to place the cells correctly. Now with a compliant layout, checks were made to see if the constraints made at the micro level really do ensure a fully compliant layout on the whole chip and if the coloring engine could cope with such large datasets. A production worthy double patterning engine is ideally distributable over multiple processors [6,7] so that fast turn-around time can be achievable on even the largest designs. We demonstrate the degree of linearity of scaling achievable with our double patterning engine. These results can be understood together with metrics such as the distribution of the sizes of networks requiring coloring resulting from these designs.

Paper Details

Date Published: 12 March 2009
PDF: 7 pages
Proc. SPIE 7275, Design for Manufacturability through Design-Process Integration III, 72751K (12 March 2009); doi: 10.1117/12.815213
Show Author Affiliations
Christopher Cork, Synopsys SARL (France)
Kevin Lucas, Synopsys, Inc. (United States)
John Hapli, Synopsys Canada (Canada)
Herve Raffard, Synopsys SARL (France)
Levi Barnes, Synopsys Technology Park (United States)

Published in SPIE Proceedings Vol. 7275:
Design for Manufacturability through Design-Process Integration III
Vivek K. Singh; Michael L. Rieger, Editor(s)

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