As the semiconductor industry moves to the 45nm node and beyond, the tolerable lithography process window significantly shrinks due to the combined use of high NA and low k1 factor. This is exacerbated by the fact that the usable depth of focus at 45nm node for critical layer is 200nm or less. Traditional Optical Proximity Correction (OPC) only computes the optimal pattern layout to optimize its lithography patterning at nominal process condition (nominal defocus and nominal exposure dose) according to an OPC model calibrated at this nominal condition, and this may put the post-OPC layout at non-negligible patterning failure risk due to the inevitable process variation (mainly defocus and dose variations). With a little sacrifice at the nominal condition, process variation aware OPC can greatly enhance the robustness of post-OPC layout patterning in the presence of defocus and dose variation. There is also an increasing demand for through process window lithography verification for post-OPC circuit layout. The corner stone for successful process variation aware OPC and lithography verification is an accurately calibrated continuous process window model which is a continuous function of defocus and dose. This calibrated model needs to be able to interpolate and extrapolate in the usable process window. Based on Synopsys' OPC modeling software package-ProGen and ProGenPlus, we developed an automated process window (PW) modeling module, which can build process variation aware process window OPC model with continuously adjustable process parameters: defocus and dose. The calibration of this continuous PW model was performed in a single calibration process using silicon measurement at nominal condition and off-focus-off-dose conditions. Through the example of several process window models for layers at 45nm technology nodes, we demonstrated that this novel continuous PW modeling approach can achieve very good performance both at nominal condition and at interpolated or extrapolated off-focus-off-dose conditions.

Date Published: 12 March 2009
PDF: 10 pages
Proc. SPIE 7275, Design for Manufacturability through Design-Process Integration III, 72751J (12 March 2009); doi: 10.1117/12.815094

Published in SPIE Proceedings Vol. 7275:
Design for Manufacturability through Design-Process Integration III
Vivek K. Singh; Michael L. Rieger, Editor(s)