Share Email Print

Proceedings Paper

Improving capability of recipe management on CD-SEM using recipe diagnostic tool
Author(s): Kaoru Nishiuchi; Shinichi Nakano; Masaki Nishino; Kyoungmo Yang; Junichi Kakuta; Yukari Nakata; Shunsuke Koshihara
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

In the semiconductor manufacturing industry, CD-SEM (Critical Dimension - Scanning Electron Microscope) is used for CD measurements on semiconductor wafers. In the CD-SEM, there is a program called "recipe" which is a series of files containing information on measurement conditions (i.e. where, how and what to measure). The recipe controls all of the parameters such as auto focus, pattern recognition and measurement parameters. Depending on the quality of this recipe, there is the possibility of errors in auto focus, pattern recognition and measurements. There are many ways in which to improve the quality of the recipe for better productivity. One method to obtain a higher quality recipe requires the use of a wafer and CD-SEM. When optimizing the recipe, the quality of improvements to the recipe depend heavily on the skill of the engineer, and wafer and CD-SEM conditions. In the semiconductor manufacturing Fab it is very time consuming to optimize recipe errors, as it requires wafer availability, arranging CDSEM tool time, and analysis of root course of error. This paper discusses a recipe diagnostic tool to evaluate and analyze the root cause of recipe errors. This tool can provide not only analysis of the error root cause, but can also help the user determine how to improve the recipe quality by pinpointing the problematic recipe parameters. This will allow the user to properly select the parameters that need adjustment in order to obtain the best performance recipe possible. This method can reduce engineering time for recipe control by a factor of 10.

Paper Details

Date Published: 23 March 2009
PDF: 10 pages
Proc. SPIE 7272, Metrology, Inspection, and Process Control for Microlithography XXIII, 72722F (23 March 2009); doi: 10.1117/12.814972
Show Author Affiliations
Kaoru Nishiuchi, Panasonic Corp. (Japan)
Shinichi Nakano, Panasonic Semiconductor Engineering Co.,Ltd. (Japan)
Masaki Nishino, Panasonic Semiconductor Engineering Co.,Ltd. (Japan)
Kyoungmo Yang, Hitachi High-Technologies Corp. (Japan)
Junichi Kakuta, Hitachi High-Technologies Corp. (Japan)
Yukari Nakata, Hitachi High-Technologies Corp. (Japan)
Shunsuke Koshihara, Hitachi High-Technologies Corp. (Japan)

Published in SPIE Proceedings Vol. 7272:
Metrology, Inspection, and Process Control for Microlithography XXIII
John A. Allgair; Christopher J. Raymond, Editor(s)

© SPIE. Terms of Use
Back to Top
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?