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Proceedings Paper

Simplify to survive: prescriptive layouts ensure profitable scaling to 32nm and beyond
Author(s): Lars Liebmann; Larry Pileggi; Jason Hibbeler; Vyacheslav Rovner; Tejas Jhaveri; Greg Northrop
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Paper Abstract

The time-to-market driven need to maintain concurrent process-design co-development, even in spite of discontinuous patterning, process, and device innovation is reiterated. The escalating design rule complexity resulting from increasing layout sensitivities in physical and electrical yield and the resulting risk to profitable technology scaling is reviewed. Shortcomings in traditional Design for Manufacturability (DfM) solutions are identified and contrasted to the highly successful integrated design-technology co-optimization used for SRAM and other memory arrays. The feasibility of extending memory-style design-technology co-optimization, based on a highly simplified layout environment, to logic chips is demonstrated. Layout density benefits, modeled patterning and electrical yield improvements, as well as substantially improved layout simplicity are quantified in a conventional versus template-based design comparison on a 65nm IBM PowerPC 405 microprocessor core. The adaptability of this highly regularized template-based design solution to different yield concerns and design styles is shown in the extension of this work to 32nm with an increased focus on interconnect redundancy. In closing, the work not covered in this paper, focused on the process side of the integrated process-design co-optimization, is introduced.

Paper Details

Date Published: 12 March 2009
PDF: 9 pages
Proc. SPIE 7275, Design for Manufacturability through Design-Process Integration III, 72750A (12 March 2009); doi: 10.1117/12.814701
Show Author Affiliations
Lars Liebmann, IBM Microelectronics (United States)
Larry Pileggi, PDF Solutions (United States)
Jason Hibbeler, IBM Microelectronics (United States)
Vyacheslav Rovner, PDF Solutions (United States)
Tejas Jhaveri, PDF Solutions (United States)
Greg Northrop, IBM Microelectronics (United States)


Published in SPIE Proceedings Vol. 7275:
Design for Manufacturability through Design-Process Integration III
Vivek K. Singh; Michael L. Rieger, Editor(s)

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