
Proceedings Paper
Tiny footprint programmable electrical defocus monitorsFormat | Member Price | Non-Member Price |
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Paper Abstract
A tiny footprint electrically probable single layer defocus monitor/test structure has been designed and tested to show
sub-10nm resolution in electrical or electronic defocus monitoring. Electronic testing is a low-cost must have for on-chip
production process monitoring which will become necessary for effective Design for Manufacturing. This programmable
defocus monitor can be designed to pinch open at various levels of defocus by modifying four different layout
parameters, CD, probe size, offset, and the number of rings. An array of these structures can be read as a series of opens
and shorts, or 1s and 0s, to electronically extract defocus. One important feature of this defocus test structure is that it has
an asymmetric response through focus, which translates to a high sensitivity to defocus at low defocus values or close to
nominal conditions. Simulation and experimental results have shown good sensitivity for both on axis, tophat, and offaxis,
quasar, illumination. This paper will present both simulation and experimental results that demonstrate the
programmability and sensitivity of this test structure to defocus.
Paper Details
Date Published: 12 March 2009
PDF: 12 pages
Proc. SPIE 7275, Design for Manufacturability through Design-Process Integration III, 727507 (12 March 2009); doi: 10.1117/12.814448
Published in SPIE Proceedings Vol. 7275:
Design for Manufacturability through Design-Process Integration III
Vivek K. Singh; Michael L. Rieger, Editor(s)
PDF: 12 pages
Proc. SPIE 7275, Design for Manufacturability through Design-Process Integration III, 727507 (12 March 2009); doi: 10.1117/12.814448
Show Author Affiliations
Wojtek Poppe, Univ. of California, Berkeley (United States)
Patrick Au, Univ. of California, Berkeley (United States)
Darshana Jayasuriya, Univ. of California, Berkeley (United States)
Patrick Au, Univ. of California, Berkeley (United States)
Darshana Jayasuriya, Univ. of California, Berkeley (United States)
Juliet Rubinstein, Univ. of California, Berkeley (United States)
Andrew R. Neureuther, Univ. of California, Berkeley (United States)
Andrew R. Neureuther, Univ. of California, Berkeley (United States)
Published in SPIE Proceedings Vol. 7275:
Design for Manufacturability through Design-Process Integration III
Vivek K. Singh; Michael L. Rieger, Editor(s)
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