When the VLSI technology scales down to sub 40nm process node, the application of EUV is still far from reality, which forces 193nm ArF light source to be used at 32nm/22nm node. This large gap causes severe light refraction and hence reliable printing becomes a huge challenge. Various resolution enhancement technologies (RETs) have been introduced in order to solve this manufacturability problem, but facing the continuously shrinking VLSI feature size, RETs will not be able to conquer the difficulties by themselves. Since layout patterns also have a strong relationship with their own printability, therefore litho-friendly design methodology with process concern becomes necessary. In the very near future, double patterning technology (DPT) will be needed in the 32nm/22nm node, and this new process will bring major change to the circuit design phases for sure. In this paper, we try to solve the printability problem at the cell design level. Instead of the conventional 2-D structure of the standard cell, we analyze the trend of the application of 1-D cell based on three emerging double patterning technologies. Focusing on the dense line printing technology with off-axis illumination, line-end gap distribution is studied to guide our methodology for optimal cell design.

Date Published: 12 March 2009
PDF: 8 pages
Proc. SPIE 7275, Design for Manufacturability through Design-Process Integration III, 72751G (12 March 2009); doi: 10.1117/12.814445

Published in SPIE Proceedings Vol. 7275:
Design for Manufacturability through Design-Process Integration III
Vivek K. Singh; Michael L. Rieger, Editor(s)