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Proceedings Paper

Full flow for transistor simulation based on edge-contour extraction and advanced SPICE simulation
Author(s): Eitan Shauly; Andres Torres; Loran Friedrich; Moran Cohen-Yasour; Ovadya Menadeva; Fedor Pikus
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Paper Abstract

A methodology for predicting on and off-state transistor performance is described in this paper. In general, this flow consists of systematic Edge-Contour-Extraction (ECE) from devices under the manufacturing, followed by device simulation. Gate parameter extraction calculates an equivalent gate length and width (Leq, Weq) for non-rectangular gates. The methodology requires a model describing MOSFET behavior of current versus width for various gate lengths and voltages. Non-rectangular gates are described by a weighted sum of the currents from a discrete representation (i.e. Total gate current is determined by a weighted sum since the current distribution is not homogeneous along the channel). Thus, for a given L, W and V, the current should be discoverable from the calibrated model. This approach is more general than previous work as both Leq and Weq are determined for a given voltage which permits the model to predict on and off-current with a single spice netlist as opposed to previous work which only considered adjustments to the channel length. In this work, two transistor series at two different drawn pitch conditions (dense and isolated) were manufactured, followed by state-of-the-art ECE. The contours obtained directly by SEM measurements were used to perform an electrical device simulation for each individual transistor in the series. This paper demonstrates the possibility to analyze the transistor's electrical performance at nominal and off-process conditions. The presented simulation flow provides the advantage of early-in-time prediction of the transistor performances, measuring large volume of devices in a fast and accurate fashion.

Paper Details

Date Published: 12 March 2009
PDF: 9 pages
Proc. SPIE 7275, Design for Manufacturability through Design-Process Integration III, 727519 (12 March 2009); doi: 10.1117/12.814361
Show Author Affiliations
Eitan Shauly, Tower Semiconductor (Israel)
Andres Torres, Mentor Graphics Corp. (United States)
Loran Friedrich, Mentor Graphics Corp. (United States)
Moran Cohen-Yasour, Tower Semiconductor (Israel)
Ovadya Menadeva, Applied Materials, Inc. (Israel)
Fedor Pikus, Mentor Graphics Corp. (United States)

Published in SPIE Proceedings Vol. 7275:
Design for Manufacturability through Design-Process Integration III
Vivek K. Singh; Michael L. Rieger, Editor(s)

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