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Proceedings Paper

Variability aware interconnect timing models for double patterning
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Paper Abstract

A compact model for estimating delay variations due to double patterning lithography process variations on interconnect layers is presented. Through process simulation and circuit analysis of one-dimensional interconnect topologies, the delay response from focus, exposure, and overlay is studied. Using a process window defined by 10% linewidth change from focus and exposure, and ±10% overlay error, a worst case change in delay of 3.9% is observed for an optimal buffer circuit. It is shown that such delay responses can be modeled using a second order polynomial function of process parameters. The impact of multiple interconnect variations in unique layout environments is studied using multiple segments of interconnects each experiencing different variations. The overall delay responses are then examined, and it is shown that for these layout structures, the separate variations combine in a manner that is both additive and subtractive, thereby reducing the overall delay variations.

Paper Details

Date Published: 12 March 2009
PDF: 9 pages
Proc. SPIE 7275, Design for Manufacturability through Design-Process Integration III, 727513 (12 March 2009); doi: 10.1117/12.814281
Show Author Affiliations
Eric Y. Chin, Univ. of California, Berkeley (United States)
Andrew R. Neureuther, Univ. of California, Berkeley (United States)

Published in SPIE Proceedings Vol. 7275:
Design for Manufacturability through Design-Process Integration III
Vivek K. Singh; Michael L. Rieger, Editor(s)

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