Share Email Print

Proceedings Paper

Parameter-specific electronic measurement and analysis of sources of variation using ring oscillators
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

Parameter-specific and simulation-calibrated ring oscillator (RO) inverter layouts are described for identifying and quantitatively modeling sources of circuit performance variation from source/drain stress, shallow trench isolation (STI) stress, lithography, etch, and misalignment. This paper extends the RO approach by adding physical modeling/simulation of the sources of variability to tune the layouts of monitors for enhanced sensitivity and selectivity. Poly and diffusion layout choices have been guided by fast-CAD pattern matching. The accuracy of the fast-CAD estimate from the Pattern Matcher for these lithography issues is corroborated by simulations in Mentor Graphics Calibre. Generic conceptual results are given based on the experience from preparing of proprietary layouts that pass DRC check for a 45 nm test chip with ST Micro. Typical improvements in sensitivity of 2 fold are possible with layouts for lithography focus. A layout monitor for poly to diffusion misalignment based on programmable off-sets shows a 0.8% change in RO frequency per 1nm poly to diffusion off-set. Layouts are also described for characterizing stress effects associated with diffusion area size, asymmetry, vertical spacing, and multiple gate lengths.

Paper Details

Date Published: 12 March 2009
PDF: 10 pages
Proc. SPIE 7275, Design for Manufacturability through Design-Process Integration III, 72750L (12 March 2009); doi: 10.1117/12.814227
Show Author Affiliations
Lynn T.-N. Wang, Univ. of California, Berkeley (United States)
Liang-Teck Pang, Univ. of California, Berkeley (United States)
IBM T. J. Watson Research Ctr. (United States)
Andrew R. Neureuther, Univ. of California, Berkeley (United States)
Borivoje Nikolić, Univ. of California, Berkeley (United States)

Published in SPIE Proceedings Vol. 7275:
Design for Manufacturability through Design-Process Integration III
Vivek K. Singh; Michael L. Rieger, Editor(s)

© SPIE. Terms of Use
Back to Top