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Proceedings Paper

Hierarchical modeling of spatial variability with a 45nm example
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Paper Abstract

In previous publications we have proposed a hierarchical variability model and verified it with 90nm test data. This model is now validated with a new set of 45nm test chips. A mixed sampling scheme with both sparse and exhaustive measurements is designed to capture both wafer level and chip level variations. Statistical analysis shows that the acrosswafer systematic function can be sufficiently described as parabolic, while the within-die systematic variation is now very small, with no discernible systematic component. Analysis of pattern dependent effects on leakage current shows that systematic pattern-to-pattern LEFF variation is almost eliminated by optical proximity correction (OPC), but stressrelated variation is not. Intentionally introduced gate length offset between two wafers in our dataset provides insight to device parameter variability and sheds additional light on the underlying sources of process variation.

Paper Details

Date Published: 6 March 2009
PDF: 12 pages
Proc. SPIE 7275, Design for Manufacturability through Design-Process Integration III, 727505 (6 March 2009); doi: 10.1117/12.814226
Show Author Affiliations
Kun Qian, Univ. of California, Berkeley (United States)
Borivoje Nikolić, Univ. of California, Berkeley (United States)
Costas J. Spanos, Univ. of California, Berkeley (United States)

Published in SPIE Proceedings Vol. 7275:
Design for Manufacturability through Design-Process Integration III
Vivek K. Singh; Michael L. Rieger, Editor(s)

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