A novel model-based algorithm provides a capability to control full-chip design specific variation in pattern transfer caused by via/contact etch processes. This physics based algorithm is capable of detecting and reporting etch hotspots based on the fab defined thresholds of acceptable variations in critical dimension (CD) of etched shapes. It can be used also as a tool for etch process optimization to capture the impact of a variety of patterns presented in a particular design. A realistic set of process parameters employed by the developed model allows using this novel via-contact etch (VCE) EDA tool for the design aware process optimization in addition to the "standard" process aware design optimization.

Date Published: 12 March 2009
PDF: 12 pages
Proc. SPIE 7275, Design for Manufacturability through Design-Process Integration III, 72750H (12 March 2009); doi: 10.1117/12.813882

Published in SPIE Proceedings Vol. 7275:
Design for Manufacturability through Design-Process Integration III
Vivek K. Singh; Michael L. Rieger, Editor(s)