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Proceedings Paper

Using intrafield high-order correction to achieve overlay requirement beyond sub-40nm node
Author(s): Chun Yen Huang; Chuei Fu Chue; An-Hsiung Liu; Wen Bin Wu; Chiang Lin Shih; Tsann-Bim Chiou; Juno Lee; Owen Chen; Alek Chen
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Paper Abstract

Overlay requirements for semiconductor devices are getting more demanding as the design rule shrinks. According to ITRS expectation[1], on product overlay budget is less than 8nm for the DRAM 40nm technology node. In order to meet this requirement, all overlay error sources have to be analyzed and controlled which include systematic, random, even intrafield high order errors. In this paper, we studied the possibility of achieving <7nm overlay control in mass production by using CPE, Correction Per Exposure mode, and Intra-field high order correction (i-HOPC). CPE is one of the functions in GridMapper package, which is a method to apply correction for each exposure to compensate both systematic and random overlay errors. If the intra-field overlay shows a non-linear fingerprint, e.g. due to either wafer processing or reticle pattern placement errors, the intra-field High Order Process Correction(iHOPC) provided by ASML can be used to compensate for this error . We performed the experiments on an immersion tool which has the GridMapper functionality. In our experiment, the previous layer was exposed on a dry machine. The wet to dry matching represent a more realistic scanner usage in the fab enviroment. Thus, the results contained the additional contribution of immersion-to-dry matched machine overlay. Our test result shows that the overlay can be improved by 70%, and the mean+3sigma of full wafer measurement can achieve near the range of 6 to 5nm. In this paper we also discuss the capability of implementation of CPE in the mass production environment since CPE requires additional wafer mearurement to create the proper overlay correction.

Paper Details

Date Published: 23 March 2009
PDF: 9 pages
Proc. SPIE 7272, Metrology, Inspection, and Process Control for Microlithography XXIII, 72720I (23 March 2009); doi: 10.1117/12.813628
Show Author Affiliations
Chun Yen Huang, Nanya Technology Corp. (Taiwan)
Chuei Fu Chue, Nanya Technology Corp. (Taiwan)
An-Hsiung Liu, Nanya Technology Corp. (Taiwan)
Wen Bin Wu, Nanya Technology Corp. (Taiwan)
Chiang Lin Shih, Nanya Technology Corp. (Taiwan)
Tsann-Bim Chiou, ASML Technology Development Ctr. (Taiwan)
Juno Lee, ASML Center of Excellence (ACE) (Taiwan)
Owen Chen, ASML Center of Excellence (ACE) (Taiwan)
Alek Chen, ASML Technology Development Ctr. (Taiwan)

Published in SPIE Proceedings Vol. 7272:
Metrology, Inspection, and Process Control for Microlithography XXIII
John A. Allgair; Christopher J. Raymond, Editor(s)

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