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Proceedings Paper

A new method for post-etch OPC modeling to compensate for underlayer effects from integrated wafers
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Paper Abstract

In this paper, we demonstrate a new methodology for post-etch OPC modeling to compensate for effects of underlayer seen on product wafers. Current resist-only OPC models based on data from flopdown wafers are not always accurate enough to deliver patterning solutions with stringent critical dimension requirements in 45/32nm technology node. Therefore it is necessary to include an etch model into the OPC correction. Both litho and etch model were built using flopdown and integrated wafers to compensate for topography, differential etch due to different underlayer substrate based on local geometry and local loading. The wafer data based on such OPC keyword show significant decrease of critical dimensions offsets of device macros from long poly-line nested structures for gate level. We will compare wafer data from two different OPC model versions built from flopdown and integrated wafer. We will also discuss modeling options in terms of two layer test masks for future technologies.

Paper Details

Date Published: 16 March 2009
PDF: 9 pages
Proc. SPIE 7274, Optical Microlithography XXII, 72740Z (16 March 2009); doi: 10.1117/12.813546
Show Author Affiliations
Chandra Sarma, Infineon Technologies NA (United States)
Amr Abdo, IBM Microelectronics (United States)
Derren Dunn, IBM Microelectronics (United States)
Daniel Fischer, IBM Microelectronics (United States)
Klaus Herold, Infineon Technologies NA (United States)
Scott Mansfield, IBM Microelectronics (United States)
Len Tsou, IBM Microelectronics (United States)

Published in SPIE Proceedings Vol. 7274:
Optical Microlithography XXII
Harry J. Levinson; Mircea V. Dusa, Editor(s)

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