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Proceedings Paper

Practical implementation of via and wire optimization at the SoC level
Author(s): Chi-Min Yuan; Guy Assad; Bob Jarvis; Marc Olivares; Lionel Riviere Cazaux; Puneet Sharma; Jayathi Subramanian; Matt Thompson; Kevin Wu
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Paper Abstract

In recent years, various DFM techniques are developed and adopted by the designers to improve circuit yield and reliability. The benefits from applying a DFM technique to a circuit often come at the expense of degrading other process or design attributes. In this paper, we discuss two widely deployed techniques: double vias and wire spreading/widening, show the benefits and trade-offs of their usage, and practical ways to implement them in SoC designs.

Paper Details

Date Published: 12 March 2009
PDF: 8 pages
Proc. SPIE 7275, Design for Manufacturability through Design-Process Integration III, 72750S (12 March 2009); doi: 10.1117/12.813396
Show Author Affiliations
Chi-Min Yuan, Freescale Semiconductor, Inc. (United States)
Guy Assad, Freescale Semiconductor, Inc. (United States)
Bob Jarvis, Freescale Semiconductor, Inc. (United States)
Marc Olivares, Freescale Semiconductor, Inc. (United States)
Lionel Riviere Cazaux, Freescale Semiconductor, Inc. (United States)
Puneet Sharma, Freescale Semiconductor, Inc. (United States)
Jayathi Subramanian, Freescale Semiconductor, Inc. (United States)
Matt Thompson, Freescale Semiconductor, Inc. (United States)
Kevin Wu, Freescale Semiconductor, Inc. (United States)


Published in SPIE Proceedings Vol. 7275:
Design for Manufacturability through Design-Process Integration III
Vivek K. Singh; Michael L. Rieger, Editor(s)

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