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Proceedings Paper

Optimization of photodetector thickness in vertically-integrated image sensors
Author(s): Orit Skorka; Dan Sirbu; Dileepan Joseph
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Paper Abstract

There is an emerging interest in vertically-integrated CMOS (VI-CMOS) image sensors. This trend arises from the difficulty in achieving high SNR, high dynamic range, and high frame rate with planar technologies while maintaining small pixel sizes, since the photodetector and electronics have to share the same pixel area and use the same technology. Fabrication methods for VI-CMOS image sensors add new degrees of freedom to the photodetector design. Having a model that gives a good approximation to the behavior of a device under different operating conditions is important for device optimization. This work presents a new approach in photodetector modeling, and uses it to optimize the thickness of the photosensitive layer in VI-CMOS image sensors. We consider a simplified structure of an a-Si:H photodetector, and develop an analytical solution and a numerical solution to state equations taken from semiconductor physics, which are shown to be comparable. If the photosensitive layer is too thin, our model shows that the contact resistances dominate the device and, if it is too thick, most charge carriers recombine on their way to the contacts. Therefore, an optimum thickness can be found.

Paper Details

Date Published: 27 January 2009
PDF: 12 pages
Proc. SPIE 7249, Sensors, Cameras, and Systems for Industrial/Scientific Applications X, 72490O (27 January 2009); doi: 10.1117/12.805999
Show Author Affiliations
Orit Skorka, Univ. of Alberta (Canada)
Dan Sirbu, Univ. of Alberta (Canada)
Dileepan Joseph, Univ. of Alberta (Canada)

Published in SPIE Proceedings Vol. 7249:
Sensors, Cameras, and Systems for Industrial/Scientific Applications X
Erik Bodegom; Valérie Nguyen, Editor(s)

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