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Proceedings Paper

Mask specification guidelines in spacer patterning technology
Author(s): Kohji Hashimoto; Hidefumi Mukai; Seiro Miyoshi; Shinji Yamaguchi; Hiromitsu Mashita; Yuuji Kobayashi; Kenji Kawano; Takashi Hirano
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Paper Abstract

We have studied both the mask CD specification and the mask defect specification for spacer patterning technology (SPT). SPT has the possibility of extending optical lithography to below 40nm half-pitch devices. Since SPT necessitates somewhat more complicated wafer process flow, the CD error and mask defect printability on wafers involve more process factors compared with conventional single-exposure process (SEP). This feature of SPT implies that it is very important to determine mask-related specifications for SPT in order to select high-end mask fabrication strategies; those are for mask writing tools, mask process development, materials, inspection tools, and so on. Our experimental studies reveal that both mask CD specification and mask defect specification are somehow relaxed from those in ITRS2007. This is most likely because SPT reduces mask CD error enhanced factor (MEF) and the reduction of line-width roughness (LWR).

Paper Details

Date Published: 4 December 2008
PDF: 10 pages
Proc. SPIE 7140, Lithography Asia 2008, 714022 (4 December 2008); doi: 10.1117/12.804744
Show Author Affiliations
Kohji Hashimoto, Toshiba Corp. (Japan)
Hidefumi Mukai, Toshiba Corp. (Japan)
Seiro Miyoshi, Toshiba Corp. (Japan)
Shinji Yamaguchi, Toshiba Corp. (Japan)
Hiromitsu Mashita, Toshiba Corp. (Japan)
Yuuji Kobayashi, Toshiba Corp. (Japan)
Kenji Kawano, Toshiba Corp. (Japan)
Takashi Hirano, Toshiba Corp. (Japan)

Published in SPIE Proceedings Vol. 7140:
Lithography Asia 2008
Alek C. Chen; Burn Lin; Anthony Yen, Editor(s)

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