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Proceedings Paper

CD uniformity improvement of sub 60nm contact hole using model based OPC
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Paper Abstract

Generally, rule based optical proximity correction (OPC) together with conventional illumination is used for contact layers, because it is simple to handle and processing times are short. As the design rule is getting smaller, it becomes more difficult to accurately control critical dimension (CD) variation because of influence by nearby contact holes pattern. Especially, random contact hole shows greater amount of CD difference between X and Y direction compared to array contact holes. Several resolution enhancement techniques (RET) were used to resolve this kind of problem, but didn't meet the overall expectations. In this paper, we will present the results for novel contact hole model-based OPC for sub 60nm memory device. First, model calibration method will be proposed for contact holes pattern, which utilizes two thousands of real contact holes pattern to improve model accuracy in full chip. Second, verification method will be proposed to check weak points on full chip using model based verification. Finally, method for further enhancing CD variation within 5nm for model based OPC will be discussed using Die-to-Database Verification.

Paper Details

Date Published: 4 December 2008
PDF: 8 pages
Proc. SPIE 7140, Lithography Asia 2008, 71403E (4 December 2008); doi: 10.1117/12.804654
Show Author Affiliations
Hyoung-Soon Yune, Hynix Semiconductor Inc. (South Korea)
Yeong-Bae Ahn, Hynix Semiconductor Inc. (South Korea)
Jung-Chan kim, Hynix Semiconductor Inc. (South Korea)
Hye-Jin Shin, Hynix Semiconductor Inc. (South Korea)
Gyun Yoo, Hynix Semiconductor Inc. (South Korea)
James Moon, Hynix Semiconductor Inc. (South Korea)
Byoung-Sub Nam, Hynix Semiconductor Inc. (South Korea)
Donggyu Yim, Hynix Semiconductor Inc. (South Korea)

Published in SPIE Proceedings Vol. 7140:
Lithography Asia 2008
Alek C. Chen; Burn Lin; Anthony Yen, Editor(s)

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