
Proceedings Paper
Non-uniform yield optimization for integrated circuit layout considering global interactionsFormat | Member Price | Non-Member Price |
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Paper Abstract
In a previous work we have shown a yield optimization metric and a technique that considers the effects of several
types of yield enhancement methods for a given layout. Those findings suggested that it is important to consider two
types of yield tradeoffs, local tradeoffs where addressing one yield loss mechanism degrades others in the immediate
vicinity of the correction (local optimization window), and global tradeoffs where the net effect of the correction can be
fully accounted only when considering neighboring optimization windows. Such conclusion was derived from the fact
that the locally optimized layouts did not completely realize the theoretically optimal yield, which was obtained from
the assumption that global tradeoffs could be fully resolved. This work focuses in the contribution that such global
tradeoffs have on the final yield score when accounted properly during the optimization.
While the previous work focused only in selecting the corrections that locally improved the yield score1, this work
evaluates the global interactions before and after a change, and the correction is only accepted if it improves the global
score. While the global optimization requires a more expensive computational process, the intention of this work is to
determine how close the optimal layout can be from its theoretical limit. Since the optimization is performed and
evaluated under four different types of processes in which the failure mechanisms vary in relative importance, it is
possible to derive conclusions as to the need of considering global effects when trading off runtime requirements with
quality of the correction.
Paper Details
Date Published: 17 October 2008
PDF: 8 pages
Proc. SPIE 7122, Photomask Technology 2008, 71223R (17 October 2008); doi: 10.1117/12.801144
Published in SPIE Proceedings Vol. 7122:
Photomask Technology 2008
Hiroichi Kawahira; Larry S. Zurbrick, Editor(s)
PDF: 8 pages
Proc. SPIE 7122, Photomask Technology 2008, 71223R (17 October 2008); doi: 10.1117/12.801144
Show Author Affiliations
J. Andres Torres, Mentor Graphics Corp. (United States)
Fedor G. Pikus, Mentor Graphics Corp. (United States)
Published in SPIE Proceedings Vol. 7122:
Photomask Technology 2008
Hiroichi Kawahira; Larry S. Zurbrick, Editor(s)
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