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Proceedings Paper

Process control for 45 nm CMOS logic gate patterning
Author(s): Bertrand Le Gratiet; Pascal Gouraud; Enrique Aparicio; Laurene Babaud; Karen Dabertrand; Mathieu Touchet; Stephanie Kremer; Catherine Chaton; Franck Foussadier; Frank Sundermann; Jean Massin; Jean-Damien Chapon; Maxime Gatefait; Blandine Minghetti; Jean de-Caunes; Daniel Boutin
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Paper Abstract

This paper present an evaluation of our CMOS 45nm gate patterning process performance based on immersion lithography in a production environment. A CD budget breakdown is shown detailing lot to lot, wafer to wafer, intrawafer, intrafield and proximity CD uniformity characterization. Emphasis is given on scatterometry library development and deployment. We also look more into detail to focus effect on CD control. Finally status of overlay performance with immersion lithography is also presented.

Paper Details

Date Published: 22 March 2008
PDF: 11 pages
Proc. SPIE 6922, Metrology, Inspection, and Process Control for Microlithography XXII, 69220Z (22 March 2008); doi: 10.1117/12.776889
Show Author Affiliations
Bertrand Le Gratiet, STMicroelectronics (France)
Pascal Gouraud, STMicroelectronics (France)
Enrique Aparicio, STMicroelectronics (France)
Laurene Babaud, STMicroelectronics (France)
Karen Dabertrand, STMicroelectronics (France)
Mathieu Touchet, STMicroelectronics (France)
Stephanie Kremer, KLA-Tencor (France)
Catherine Chaton, CEA-Leti (France)
Franck Foussadier, STMicroelectronics (France)
Frank Sundermann, STMicroelectronics (France)
Jean Massin, STMicroelectronics (France)
Jean-Damien Chapon, STMicroelectronics (France)
Maxime Gatefait, STMicroelectronics (France)
Blandine Minghetti, STMicroelectronics (France)
Jean de-Caunes, STMicroelectronics (France)
Daniel Boutin, STMicroelectronics (France)

Published in SPIE Proceedings Vol. 6922:
Metrology, Inspection, and Process Control for Microlithography XXII
John A. Allgair; Christopher J. Raymond, Editor(s)

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