Share Email Print

Proceedings Paper

A method of obtaining optical lithography friendly layout using a model for first level defects
Author(s): Sungsoo Suh; Sukjoo Lee
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

During early stage of a memory device development, photolithography engineer provide a lithography friendly layout to a designer and assist in development of design rule. Most of the cases, lithographer relies on the accuracy of lithography simulator to generate some guidelines and/or modifications to a designer which may be sufficient for a cell only design. Even for such a cell only designs, it is increasingly difficult to perform such task due to shrinkage of chip design. For some random pattern design contained in a core and periphery regions, a more rapid method of evaluating the layout is needed. In order to perform a fast evaluation, a calibrated proximity model is needed. If a calibration data is available, a layout can be OPCed and verified to detect weak spots. On the other hand, a calibration data may not be available during early design stage. In this paper, a method of obtaining lithography model without the need of calibration data is presented. First, an illumination source optimization is performed on the specific patterns to minimize the effect of critical dimension variation. Using the illumination condition obtained, an optical model is used to determine the first level layout weak spots which are most critical to a specific layer type based on the image quality analysis. At this point, one may choose to perform OPC using the optical model and analyze the process margin. A further interest is on whether if a particular model can by-pass the need for OPC layout in verifying the layout.

Paper Details

Date Published: 4 March 2008
PDF: 8 pages
Proc. SPIE 6925, Design for Manufacturability through Design-Process Integration II, 69251P (4 March 2008); doi: 10.1117/12.774098
Show Author Affiliations
Sungsoo Suh, Samsung Electronics Co., Ltd. (South Korea)
Sukjoo Lee, Samsung Electronics Co., Ltd (South Korea)

Published in SPIE Proceedings Vol. 6925:
Design for Manufacturability through Design-Process Integration II
Vivek K. Singh; Michael L. Rieger, Editor(s)

© SPIE. Terms of Use
Back to Top