Share Email Print

Proceedings Paper

Process variation in metal-oxide-metal (MOM) capacitors
Author(s): Lynn Tao-Ning Wang
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

Aerial image simulation of interdigitated sidewall capacitor layouts and extraction of feature changes are used to estimate the parametric performance spread of DC Metal-Oxide-Metal (MOM) mixed signal capacitors as a function of the normalized lithographic resolution k1. Since minimum feature sizes are utilized, the variation of MOM capacitors is attributed to lithography spacing. In this paper, k1 of 0.8, 0.56, 0.40, and 0.28 are studied. The DC capacitance shows a worst-case variability of 42%. While line-end-shortening is a small fractional change in finger length and proves to be not a critical factor in variability, spacing width proves to be the main source of the variability in DC capacitance. Different annular illumination settings are explored for mitigating the variability in spacing width. Co-design of the pitch and illumination shows that for each k1, there is an optimal annular illumination radius. The optimal set of sigmas (i.e. sigma_in and sigma_out) can control the variability between linewidths and spacing widths to 20%.

Paper Details

Date Published: 18 March 2008
PDF: 8 pages
Proc. SPIE 6925, Design for Manufacturability through Design-Process Integration II, 69251M (18 March 2008); doi: 10.1117/12.773197
Show Author Affiliations
Lynn Tao-Ning Wang, Univ. of California, Berkeley (United States)

Published in SPIE Proceedings Vol. 6925:
Design for Manufacturability through Design-Process Integration II
Vivek K. Singh; Michael L. Rieger, Editor(s)

© SPIE. Terms of Use
Back to Top
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?