Scaling of designs to the 45nm and future nodes presents challenges for block level lithography. Shrinking distances between devices drive aggressive resist placement tolerances, challenging the ability to control critical dimension (CD). In particular, the potential variation in shallow trench isolation oxide may result in variation of resist profile and CD, thereby affecting edge placement accuracy. Potential sources of this include wafer-to-wafer or within-wafer STI trench depth variations, and STI CMP variations that may be induced by active area pattern density fluctuations. Some other potential sources of CD fluctuation include oxide sidewall variation, and implant level overlay or CD errors modulating the proximity to the oxide sidewall. Depending on the actual variation of isolation oxide and the exposure latitude of the resist, the CD variations simply from oxide variation may consume a large portion of the CD budget. Several examples are given of variations in resist profile and CD arising from these substrate effects. The CD uniformity of a test structure was shown to decrease dramatically with the addition of a BARC to the resist stack, most likely due to the suppression of substrate reflectivity variations. Simulations performed using Panoramic Technologies software demonstrated the potential sensitivity of the factors outlined above on CD and profile errors. A comparison of simulated vs. experimental results is made for a case of intentional overlay error, showing the failure mode of the resist profile as the mask edge passes from STI to the active area. The simulations using a full physical model provided with the simulation software predict a resist foot forming over the active area, which was confirmed experimentally.

Date Published: 1 April 2008
PDF: 11 pages
Proc. SPIE 6924, Optical Microlithography XXI, 69244F (1 April 2008); doi: 10.1117/12.773102

Published in SPIE Proceedings Vol. 6924:
Optical Microlithography XXI
Harry J. Levinson; Mircea V. Dusa, Editor(s)