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Proceedings Paper

Microprocessor chip timing analysis using extraction of simulated silicon-calibrated contours
Author(s): Toshiaki Yanagihara; Takeshi Hamamoto; Koya Sato; Atsushi Okamura; Toshiyuki Matsunaga; Naohiro Kobayashi; Tatsuya Maekawa; Nishath Verghese; Jac Condella; Philippe Hurat
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Paper Abstract

With increasing chip sizes and shrinking device dimensions, on-chip semiconductor process variation can no longer be ignored in the design and signoff static timing analysis of integrated circuits. An important parameter affecting CMOS technologies is the gate length (Lgate) of a transistor. In modern technologies, significant spatial intra-chip variability of transistor gate lengths, which is systematic as opposed to random, can lead to relatively large variations in circuit path delays. Spatial variations in Lgate affect circuit timing properties, which can lead to timing errors and performance loss. To maximize performance and process utilization in microprocessor designs, we have developed and validated a timing analysis methodology based on accurate silicon contour prediction from drawn layout and contour-based extraction of our designs. This allows for signoff timing without unnecessarily large margins, thereby reducing chip area and maximizing performance while ensuring chip functionality, improved process utilization and yield. In this paper, we describe the chip timing methodology, its validation and implementation in microprocessor design.

Paper Details

Date Published: 4 March 2008
PDF: 11 pages
Proc. SPIE 6925, Design for Manufacturability through Design-Process Integration II, 69250O (4 March 2008);
Show Author Affiliations
Toshiaki Yanagihara, NEC Electronics Corp. (Japan)
Takeshi Hamamoto, NEC Electronics Corp. (Japan)
Koya Sato, NEC Electronics Corp. (Japan)
Atsushi Okamura, NEC Electronics Corp. (Japan)
Toshiyuki Matsunaga, NEC Electronics Corp. (Japan)
Naohiro Kobayashi, NEC Electronics Corp. (Japan)
Tatsuya Maekawa, NEC Electronics Corp. (Japan)
Nishath Verghese, Cadence Design Systems, Inc. (United States)
Jac Condella, Cadence Design Systems, Inc. (United States)
Philippe Hurat, Cadence Design Systems, Inc. (United States)

Published in SPIE Proceedings Vol. 6925:
Design for Manufacturability through Design-Process Integration II
Vivek K. Singh; Michael L. Rieger, Editor(s)

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