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Proceedings Paper

RET selection using rigorous, physics-based computational lithography
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Paper Abstract

Over the past several years, choosing the best Resolution Enhancement Technique (RET) has become more and more difficult. The RET implementation team is faced with an ever increasing number of variables to attempt to optimize. Also, for a given node, there are now more layers designated as critical pattern layers requiring RET. As design rules become more aggressive, and scanners have more process parameters such as polarization and focus drilling, RET must be optimized across a larger number of variables than before. Sorting through the best combination of all of the available process parameters could potentially require the number of wafer experiments to increase exponentially. Rigorous, physics-based computational lithography is the perfect tool for executing the large number of experiments, virtually, culling out dramatically the actual number of physical wafer experiments required for verification. Ideally, first pass RET selection needs to be made as early as possible in the technology cycle, well before the equipment is available. Traditional OPC tools, which require wafer process data to set up are not suited to this task, as they can only be used after the equipment has been installed and a stable, established process exists. Rigorous physical and chemical models, such as those found in PROLITH, are better suited to early RET selection and optimization but the Windows platform, where PROLITH is used, is computationally too slow for the massive number of calculations required. In this study, we focus on the RET selection process for a set of "typical" critical test patterns, using KLATencor's other rigorous, physics-based computational lithography tool, LithoWare. LithoWare combines the accuracy of rigorous physical and chemical models with the computational power of distributed computing on Linux. We examine the use of cluster computing in optimizing the illuminators using model based OPC and process window analysis for critical contact hole (CH) patterns. We use the results to propose a comprehensive RET selection strategy to meet the user requirements of 45nm and 32 nm development.

Paper Details

Date Published: 4 March 2008
PDF: 8 pages
Proc. SPIE 6925, Design for Manufacturability through Design-Process Integration II, 69251D (4 March 2008); doi: 10.1117/12.772872
Show Author Affiliations
Sanjay Kapasi, KLA-Tencor (United States)
Trey Graves, KLA-Tencor (United States)
Mark D. Smith, KLA-Tencor (United States)
Stewart Robertson, KLA-Tencor (United States)
Chris Sallee, KLA-Tencor (United States)

Published in SPIE Proceedings Vol. 6925:
Design for Manufacturability through Design-Process Integration II
Vivek K. Singh; Michael L. Rieger, Editor(s)

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