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Systematic yield estimation method applying lithography simulation
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Paper Abstract

In this paper, we propose the novel method quantifying impacts of lithography hot spots to chip yield with lithography simulation. Our method consists of three steps. Firstly, lithography simulation is done under several conditions including process variations, exposure dose and focus, for example. Hot spots are recognized through the results of simulations and those critical dimensions (CD) are derived. Secondly, a failure rate is calculated under a process parameter at each hot spot, respectively. Assuming the distribution of wafer CD from simulated CD, a differential failure rate on a process parameter is calculated with integrating the probability that wafer CD is less than a lower limit. Also probability that process condition is equal to the process parameter is defined from a distribution of process parameter. Finally, individual failure rate of the hot spot is calculated by summing the products of the differential failure rate and the probabilities of process parameter. Systematic yield is calculating with multiplying the differences of the individual failure rate from unity, providing that all hot spots are fully individual. An advantage of this method is that the defect probability of hot spot is calculated independently from each other and systematic yield can be easily estimated regardless of layout size, from primitive cell to full chip.

Paper Details

Date Published: 17 March 2008
PDF: 9 pages
Proc. SPIE 6925, Design for Manufacturability through Design-Process Integration II, 69250Q (17 March 2008); doi: 10.1117/12.772747
Show Author Affiliations
Suigen Kyoh, Toshiba Corp. (Japan)
Soichi Inoue, Toshiba Corp. (Japan)

Published in SPIE Proceedings Vol. 6925:
Design for Manufacturability through Design-Process Integration II
Vivek K. Singh; Michael L. Rieger, Editor(s)

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