
Proceedings Paper
Selete's EUV program: progress and challengesFormat | Member Price | Non-Member Price |
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$17.00 | $21.00 |
Paper Abstract
Selete launched a development program on EUV lithography and related mask technology in April 2006. The program is
based on the concept of "lithography design and integration." It covers a wide range of areas that require further effort to
get EUVL ready for volume production and was formulated on the basis that the issues should be considered from a
variety of standpoints, such as acceleration of the development of key lithographic components, verification that EUVL
is actually suitable for mass production, the construction of mask infrastructure, and the improvement of EUV-specific
reliability and productivity. Two exposure tools have been installed as basic infrastructure: the small-field exposure tool
(SFET) and the full-field exposure tool (EUV1). The objectives of the SFET installation are acceleration of the
development of resist materials and processes, optimization of the mask structure and materials, and the evaluation of the
exposure tool technology with regard to such things as imaging performance, stability, and the lifetimes of the optics and
source components. The objective of the EUV1 installation is to demonstrate that lithography integration is a viable path
to making EUV lithography a practical production technology. We found that the SFET provides both excellent
resolution and high tool activity. This high performance helps us to obtain a clear understanding of the current level of
EUVL performance and enables us to learn many things that can be fed back into the development program in the beta
stage. A 1st static exposure with the EUV1 resolved 30-nm dense and isolated lines and 30-nm holes. The potential
resolution was found to be as good as 28 nm. Although progress was made regarding EUV resist sensitivity and LWR,
further progress is needed. A tool for analyzing out-gassing in EUV resists was found to facilitate the development of
both resist materials and contamination control measures for exposure tools. A prototype full-field actinic inspection
system for mask blanks is now under development and should become operational in the 2Q of 2008. A mask protection
engineering (MPE) tool was used to show that a dual-pod carrier is very effective in protecting a mask from particles.
Mask pattern defect inspection technology using a DUV wavelength of 199 nm and defect repair technology based on an
FIB for EUV mask fabrication are also being developed. This work was supported in part by NEDO.
Paper Details
Date Published: 20 March 2008
PDF: 12 pages
Proc. SPIE 6921, Emerging Lithographic Technologies XII, 692102 (20 March 2008); doi: 10.1117/12.772625
Published in SPIE Proceedings Vol. 6921:
Emerging Lithographic Technologies XII
Frank M. Schellenberg, Editor(s)
PDF: 12 pages
Proc. SPIE 6921, Emerging Lithographic Technologies XII, 692102 (20 March 2008); doi: 10.1117/12.772625
Show Author Affiliations
Ichiro Mori, MIRAI-Semiconductor Leading Edge Technologies, Inc. (Japan)
Osamu Suga, MIRAI-Semiconductor Leading Edge Technologies, Inc. (Japan)
Hiroyuki Tanaka, MIRAI-Semiconductor Leading Edge Technologies, Inc. (Japan)
Iwao Nishiyama, MIRAI-Semiconductor Leading Edge Technologies, Inc. (Japan)
Tsuneo Terasawa, MIRAI-Semiconductor Leading Edge Technologies, Inc. (Japan)
Osamu Suga, MIRAI-Semiconductor Leading Edge Technologies, Inc. (Japan)
Hiroyuki Tanaka, MIRAI-Semiconductor Leading Edge Technologies, Inc. (Japan)
Iwao Nishiyama, MIRAI-Semiconductor Leading Edge Technologies, Inc. (Japan)
Tsuneo Terasawa, MIRAI-Semiconductor Leading Edge Technologies, Inc. (Japan)
Hiroyuki Shigemura, MIRAI-Semiconductor Leading Edge Technologies, Inc. (Japan)
Takao Taguchi, MIRAI-Semiconductor Leading Edge Technologies, Inc. (Japan)
Toshihiko Tanaka, MIRAI-Semiconductor Leading Edge Technologies, Inc. (Japan)
Toshiro Itani, MIRAI-Semiconductor Leading Edge Technologies, Inc. (Japan)
Takao Taguchi, MIRAI-Semiconductor Leading Edge Technologies, Inc. (Japan)
Toshihiko Tanaka, MIRAI-Semiconductor Leading Edge Technologies, Inc. (Japan)
Toshiro Itani, MIRAI-Semiconductor Leading Edge Technologies, Inc. (Japan)
Published in SPIE Proceedings Vol. 6921:
Emerging Lithographic Technologies XII
Frank M. Schellenberg, Editor(s)
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