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Proceedings Paper

DFM application on dual tone sub 50nm device
Author(s): Byoung-Sub Nam; James Moon; Joo-Hong Jung; Dong-Ho Kong; Se-young Oh; Cheol-Kyun Kim; Byung-Ho Nam; Dong Gyu Yim
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Paper Abstract

As the semiconductor feature size continues to shrink, electrical resistance issue is becoming one of the industry's dreaded problems. In order to overcome such problem, many of the top semiconductor manufacturers have turned there interest to copper process. Widely known, copper process is the trench first damascene process which utilize dark tone mask instead of widely used clear tone mask. Due to unfamiliarity and under development of dark tone mask technology compared to clear tone mask, many have reported patterning defect issues using dark tone mask. Therefore, necessity of DFM[1] for design that meets both dark and clear tone is very large in development of copper process based device. In this study, we will propose a process friendly Design For Manufacturing (DFM) rule for dual tone mask. Proposed method guides the layout rule to give same performance from both dark tone and clear tone mask from same design layout. Our proposed method will be analyzed on photolithography process margin factors such as Depth Of Focus (DOF) and Exposure Latitude (EL) on sub 50nm Flash memory interconnection layer.

Paper Details

Date Published: 19 March 2008
PDF: 7 pages
Proc. SPIE 6925, Design for Manufacturability through Design-Process Integration II, 692514 (19 March 2008); doi: 10.1117/12.772430
Show Author Affiliations
Byoung-Sub Nam, Hynix Semiconductor, Inc. (South Korea)
James Moon, Hynix Semiconductor, Inc. (South Korea)
Joo-Hong Jung, Hynix Semiconductor, Inc. (South Korea)
Dong-Ho Kong, Hynix Semiconductor, Inc. (South Korea)
Se-young Oh, Hynix Semiconductor, Inc. (South Korea)
Cheol-Kyun Kim, Hynix Semiconductor, Inc. (South Korea)
Byung-Ho Nam, Hynix Semiconductor, Inc. (South Korea)
Dong Gyu Yim, Hynix Semiconductor, Inc. (South Korea)

Published in SPIE Proceedings Vol. 6925:
Design for Manufacturability through Design-Process Integration II
Vivek K. Singh; Michael L. Rieger, Editor(s)

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