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Proceedings Paper

A procedure to back-annotate process induced layout dimension changes into the post layout simulation netlist
Author(s): Jonathan Ho; Yan Wang; Xin Wu; Jane Soward; Ping Zhang; Joanne Wu
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Paper Abstract

As transistor dimensions become smaller, on-wafer transistor dimension variations, induced by lithography or etching process, impact more to the transistor parameters than those from the earlier process technologies such as 90 nm and 130 nm. The on-wafer transistor dimension variations are layout dependent and are ignored in the standard post layout verification flow where the transistor parameters in a spice netlist are extracted from drawn transistor dimensions. There are commercial software tools for predicting the on-wafer transistor dimensions for the improved accuracy of the post-layout verification. These tools need accurate models for the on-wafer transistor dimension prediction and the models need to be re-calibrated as the fabrication process is changed. Furthermore, the model-based predictions of the on-wafer transistor dimensions require extensive computing power which can be time consuming. In the paper, a procedure to back-annotate the process induced transistor dimension changes into the post layout extracted netlist using a simple look-up table is described. The lookup table is composed of specified drawn transistor and its sounding layout as well as their on-wafer dimensions. The on-wafer dimensions can be extracted from simulations, SEM in-line pictures or electrical data of specially designed testkeys. Taking the lookup table data, accordingly, the transistor dimensions in the post-layout netlist file are then modified by a commercial software tool with a pattern search function. Comparing with the model based approach, the lookup table approach takes much less time for modifying the post-layout netlist. The lookup table approach is flexible, since the tables can be easily updated to reflect the most recent process changes from the foundry. In summary, a lookup table based approach for improving the post-layout verification accuracy is described. This approach can improve the verification accuracy from both litho and non-litho process variations. This approach has been applied to Xilinx's 65 nm and 45 nm product developments.

Paper Details

Date Published: 4 March 2008
PDF: 9 pages
Proc. SPIE 6925, Design for Manufacturability through Design-Process Integration II, 69250V (4 March 2008); doi: 10.1117/12.771427
Show Author Affiliations
Jonathan Ho, Xilinx, Inc. (United States)
Yan Wang, Xilinx, Inc. (United States)
Xin Wu, Xilinx, Inc. (United States)
Jane Soward, Xilinx, Inc. (United States)
Ping Zhang, Anchor Semiconductor, Inc. (United States)
Joanne Wu, Anchor Semiconductor, Inc. (United States)

Published in SPIE Proceedings Vol. 6925:
Design for Manufacturability through Design-Process Integration II
Vivek K. Singh; Michael L. Rieger, Editor(s)

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